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W78C52D/W78C052D 8-BIT MICROCONTROLLER
Table of Contents1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 2 PIN CONFIGURATIONS ............................................................................................................ 3 PIN DESCRIPTION..................................................................................................................... 4 FUNCTIONAL DESCRIPTION ................................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 10 DC CHARACTERISTICS.......................................................................................................... 11 AC CHARACTERISTICS .......................................................................................................... 13 TIMING WAVEFORMS ............................................................................................................. 15 APPLICATION CIRCUITS ........................................................................................................ 17 PACKAGE DIMENSIONS ......................................................................................................... 19 REVISION HISTORY ................................................................................................................ 21
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
1. GENERAL DESCRIPTION
The W78C052D microcontroller supplies a wider frequency and supply voltage range than most 8-bit microcontrollers on the market. It is compatible with the industry standard 80C52 microcontroller series. The W78C052D contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable I/O port (Port 4) and two additional external interrupts ( INT2 , INT3 ), three 16-bit timer/counters, one watchdog timer and a serial port. These peripherals are supported by a eight-source, two-level interrupt capability. There are 256 bytes of RAM and an 8K byte mask ROM for application programs. The W78C052D microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
2. FEATURES
Fully static design
Supply voltage of 4.5V to 5.5V
DC-40 MHz operation 256 bytes of on-chip scratchpad RAM 8K bytes of on-chip mask ROM 64K bytes program memory address space 64K bytes data memory address space Four 8-bit bidirectional ports Three 16-bit timer/counters One full duplex serial port
Eight-source, two-level interrupt capability
One extra 4-bit bit-addressable I/O port
Two additional external interrupts INT2 / INT3 Watchdog timer EMI reduction mode
Built-in power management Code protection Packages: - Lead Free (RoHS) DIP 40: W78C052D40DL - Lead Free (RoHS) PLCC 44: W78C052D40PL - Lead Free (RoHS) PQFP 44: W78C052D40FL
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W78C52D/W78C052D
3. PIN CONFIGURATIONS
40-Pin DIP
T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8
44-Pin PLCC
T 2 E X , PPPP 1111 .... 4321 / I A N TT D 23 0 ,, , PP P 1 4V0 . .D. 0 2D0
44-Pin QFP
T 2 E X , PPPP 1111 .... 4321 / I A N D T 0 3 , , P P 4V0 .D. 2D0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3
A D 1 , P 0 . 1
A D 2 , P 0 . 2
A D 3 , P 0 . 3 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 1 2
T 2 , P 1 . 0
P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
6 5 4 3 2 1 44 43 42 41 40 7 39 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPPP TS422 AS. . . L 001 1 ,, AA 89 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS. . L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
4. PIN DESCRIPTION
P0.0-P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory.
P1.0-P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0-P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.
P3.0-P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate functions, which are described below:
PIN ALTERNATE FUNCTION
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
RXD Serial Receive Data TXD Serial Transmit Data
INT0 External Interrupt 0 INT1 External Interrupt 1 T0 Timer 0 Input T1 Timer 1 Input WR Data Write Strobe RD Data Read Strobe
P4.0-P4.3
Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 / INT3 ).
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM. This pin should be kept low for all W78C31 operations. RST Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor. ALE Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high impedance state during reset with a weak pull-up.
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W78C52D/W78C052D
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0 address/data bus during fetch and MOVC operations. PSEN goes to a high impedance state during reset with a weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VDD
Power Supplies. These are the chip ground and positive supplies.
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
5. FUNCTIONAL DESCRIPTION
The W78C052D architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, one watchdog timer and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64 K data storage space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78C052D: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
Clock
The W78C052D is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78C052D relatively insensitive to duty cycle variations in the clock.
Crystal Oscillator
The W78C052D incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts when VDD = 5 volts.
Power Management
Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is by a reset.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C052D is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
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W78C52D/W78C052D
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts INT2 , INT3 have been added to either the PLCC or QFP package. And description follows: 1. INT2 / INT3 Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. ***XICON - external interrupt control (C0H) PX3 PX3: EX3: IE3: IT3: PX2: EX2: IE2: IT2: EX3 IE3 IT3 PX2 EX2 IE2 IT2
External interrupt 3 priority high if set External interrupt 3 enable if set If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software External interrupt 2 priority high if set External interrupt 2 enable if set If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INTERRUPT SOURCE VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL
External Interrupt 0 Timer/Counter 0 External Interrupt 1 Timer/Counter 1 Serial Port Timer/Counter 2 External Interrupt 2 External Interrupt 3
03H 0BH 13H 1BH 23H 2BH 33H 3BH
0 (highest) 1 2 3 4 5 6 7 (lowest)
IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 XICON.2 XICON.6
TCON.0 TCON.2 XICON.0 XICON.3
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
2. PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 / INT3 ). Example: P4 REG 0D8H MOV P4, #0AH ; Output data "A" through P4.0-P4.3. MOV A, P4 ; Read P4 status to Accumulator. SETB P4.0 ; Set bit P4.0 CLR P4.1 ; Clear bit P4.1
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the timeout occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different timeout values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Timer Control Register Bit: 7 ENW 6 CLRW 5 WIDL 4 Address: 8FH 3 2 PS2 1 PS1 0 PS0
Mnemonic: WDTC
ENW : Enable watch-dog if set. CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared. PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
PS2 PS1 PS0 PRESCALER SELECT
0 0 0 0 1 1 1 1
0 1 0 1 0 0 1 1
0 0 1 1 0 1 0 1
2 4 8 16 32 64 128 256
The time-out period is obtained using the following formula : -8-
W78C52D/W78C052D
1 x 2 14 x PRESCALER x 1000 x 12 mS OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset.
WIDL IDLE EXTERNAL RESET PRESCALER 14-BIT TIMER
CLEAR
ENW
OSC
1/12
INTERNAL RESET
Watchdog Timer Block Diagram
CLRW
Typical Watchdog time-out period when OSC = 20 MHz
PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD
0 0 0 0 1 1 1 1
0 1 0 1 0 0 1 1
0 0 1 1 0 1 0 1
19.66 mS 39.32 mS 78.64 mS 157.28 mS 314.57 mS 629.14 mS 1.25 S 2.50 S
Reduce EMI Emission
Because of the on-chip ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space. AUXR - Auxiliary Register Bit: 7 6 5 4 3 2 1 0 AO
Mnemonic: AUXR AO: Turn off ALE signal.
Address: 8Eh
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
6. ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN. MAX. UNIT
DC Power Supply Input Voltage Operating Temperature Storage Temperature
VCC-VSS VIN TA TST
-0.3 VSS -0.3 0 -55
+7.0 VCC +0.3 70 +150
V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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W78C52D/W78C052D
7. DC CHARACTERISTICS
Vss = 0V ; TA = 25 C; unless otherwise specified.
PARAMETER
SYM.
SPECIFICATION MIN. MAX. UNIT
TEST CONDITIONS
Operating Voltage Operating Current Idle Current Power Down Current Input Input Current P1, P2, P3, P4 Input Leakage Current P0, EA Input Current RST Logic 1-to-0 Transition Current P1, P2, P3, P4 Input Low Voltage RST Input Low Voltage P1, P2, P3, P4 Input Low Voltage XTAL1[*4] Input High Voltage P1, P2, P3, P4 Input High Voltage RST Input High Voltage XTAL1[*4]
VDD IDD IIDLE IPWDN
4.5 -
5.5 20 6 50
V mA mA A VDD = 5.5V, 20 MHz, no load VDD = 5.5V, 20 MHz, no load VDD = 5.5V, no load VDD = 5.5V VIN = 0V or VDD VDD = 5.5V VSS < VIN < VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V VIN = 2V VDD = 4.5V VDD = 4.5V VDD = 4.5V VDD = 5.5V
IIN ILK IIN2 ITL VIL2 VIL1 VIL3 VIH1 VIH2 VIH3
-50 -10 -10 -500 0 0 0 2.4 3.5 3.5
+10 +10 +300 0.8 0.8 0.8 VDD +0.2 VDD +0.2 VDD +0.2
A A A A V V V V V V
VDD = 5.5V VDD = 5.5V
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
DC Characteristics, continued
PARAMETER
SYM.
SPECIFICATION MIN. MAX. UNIT
TEST CONDITIONS
Output Output Low Voltage P1, P2, P3, P4 Output Low Voltage P0, ALE, PSEN Sink Current P1, P2, P3, P4 Sink Current P0, ALE, PSEN Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN Source Current P1, P2, P3, P4 Source Current P0, ALE, PSEN ISR2
[*4] [*4]
VOL1 VOL2 ISK1 ISK2 VOH1 VOH2 ISR1
4 8 2.4 2.4 -100 -8
0.45 0.45 8 16 -250 -14
V V mA mA V V A mA
VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +4 mA VDD = 4.5V Vin = 0.45V VDD = 4.5V VIN = 0.45V VDD = 4.5V IOH = -100 A VDD = 4.5V IOH = -400 A VDD = 4.5V VIN = 2.4V VDD = 4.5V VIN = 2.4V
Notes: *1. RST pin has an internal pull-down. *2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0. *3. RST is a Schmitt trigger input and XTAL1 is a CMOS input. *4. P0, P2, ALE and PSEN are tested in the external access mode.
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W78C52D/W78C052D
8. AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a 20 nS variation. The numbers below represent the performance expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH F OP, TCP TCL
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed Clock Period Clock High Clock Low
FOP TCP TCH TCL
0 25 10 10
-
40 -
MHz nS nS nS
1 2 3 3
Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Address Valid to ALE Low Address Hold from ALE Low ALE Low to PSEN Low
TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW
1 TCP- 1 TCP- 1 TCP- 0 0 2 TCP- 3 TCP-
2 TCP 3 TCP
2 TCP 1 TCP 1 TCP -
nS nS nS nS nS nS nS nS
4 1, 4 4 2 3 4 4
PSEN Low to Data Valid
Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width
PSEN Pulse Width
Notes: 1. P0.0-P0.7, P2.0-P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high. 4. "" (due to buffer driving delay and wire loading) is 20 nS.
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
Data Read Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
ALE Low to RD Low
RD Low to Data Valid
TDAR TDDA TDDH TDDZ TDRD
3 TCP- 0 0 6 TCP-
6 TCP
3 TCP+ 4 TCP 2 TCP 2 TCP -
nS nS nS nS nS
1, 2 1
Data Hold from RD High Data Float from RD High
RD Pulse Width
2
Notes: 1. Data memory access time is 8 TCP. 2. "" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
ALE Low to WR Low Data Valid to WR Low Data Hold from WR High
WR Pulse Width
TDAW TDAD TDWD TDWR
3 TCP- 1 TCP- 1 TCP- 6 TCP-
6 TCP
3 TCP+ -
nS nS nS nS
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE
TPDS TPDH TPDA
1 TCP 0 1 TCP
-
-
nS nS nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference.
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W78C52D/W78C052D
9. TIMING WAVEFORMS
Program Fetch Cycle
S1 XTAL1 TALW ALE TAPL PSEN TPSW TAAS PORT 2 TAAH PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 TPDA TPDH, TPDZ S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
Data Read Cycle
S4 XTAL1 ALE PSEN PORT 2 A0-A7 PORT 0 T DAR RD T DRD T DDA T DDH, T DDZ A8-A15 DATA S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
Data Write Cycle
S4 XTAL1 ALE PSEN PORT 2 PORT 0 WR
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA OUT
TDAD
T DWD
T DAW
T DWR
Port Access Cycle
S5 XTAL1 S6 S1
ALE T PDS PORT INPUT SAMPLE T PDH T PDA DATA OUT
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W78C52D/W78C052D
10. APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
V DD V DD 31 19 10 u
CRYSTAL
EA XTAL1
R 18 XTAL2 9 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
8.2 K C1 C2
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 21 22 23 24 25 26 27 28 17 16 29 30 11 10 A8 A9 A10 A11 A12 A13 A14 A15
AD0 3 AD1 4 AD2 7 AD3 8 AD413 AD514 AD617 AD718
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 A0 5 A1 6 A2 9 A3 12 A4 15 A5 16 A6 19 A7
12 13 14 15 1 2 3 4 5 6 7 8
GND 1 OC 11 G 74HC373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
GND 20 CE 22 OE 27512
W78C52D/W78C052D
Figure A
CRYSTAL
C1
C2
R
16 MHz 24 MHz 33 MHz 40 MHz
30P 15P 10P 5P
30P 15P 10P 5P
- - 6.8K 4.7K
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
Expanded External Data Memory and Oscillator
VDD VDD EA 19 XTAL1 10 u
OSCILLATOR
31
18 XTAL2 8.2 K 9 RST INT0
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 21 22 23 24 25 26 27 28 17 16 29 30 11 10 A8 A9 A10 A11 A12 A13 A14
AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 GND 1
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
12 13 INT1 14 T0 15 T1 1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 P1.6 8 P1.7
OC 11 G 74HC373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A1021 A11 23 A12 2 A1326 A14 1 GND20 22 27
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WR 20256
D0 D1 D2 D3 D4 D5 D6 D7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
W78C52D/W78C052D
Figure B
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W78C52D/W78C052D
11. PACKAGE DIMENSIONS
40-pin DIP
Symbol
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.254 3.937 4.064 5.334
D 40 21
E1
A A1 A2 B B1 c D E E1 e1 L
a
0.150 0.155 0.160 3.81
0.016 0.018 0.022 0.406 0.457 0.559 0.048 0.050 0.054 1.219 1.27 1.372
0.008 0.010 0.014 0.203 0.254 0.356 2.055 2.070 52.20 52.58
0.590 0.600 0.610 14.986 15.24 15.494 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.286 2.54 2.794
0.120 0.130 0.140 3.048 3.302 3.556 0 15 0 15
1 S A A2 L B B1 e1
20 E c A1
eA S
Notes:
0.630 0.650 0.670 16.00 16.51 17.01 0.090 2.286
Base Plane Seating Plane
eA
a
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
44-pin PLCC
HD D
6 1 44 40
Symbol Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
39
7
E
HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.185 0.020 0.026 0.028 0.032 0.508
4.699
0.145 0.150 0.155 3.683 3.81 3.937 0.66 0.711 0.813 0.016 0.018 0.022 0.406 0.457 0.559 0.008 0.010 0.014 0.203 0.254 0.356 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 BSC 0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.296 2.54 2.794 0.004 0.10
L A2 A
e
Seating Plane GD
b b1
A1 y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
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Publication Release Date: December 4, 2006 Revision A5
W78C52D/W78C052D
44-pin QFP
HD D
44 34
Dimension in inch Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
------0.02 --0.05 --0.25 2.05 --0.5 2.20 0.002 0.01
1
33
E HE
11
12
e
b
22
A A1 A2 b c D E e HD HE L L1 y
Notes:
c
0.075 0.081 0.087 1.90 0.01 0.014 0.018 0.25
0.35 0.45
0.004 0.006 0.010 0.101 0.152 0.254 0.390 0.394 0.398 9.9 0.390 0.394 0.398 9.9 10.00 10.1 10.00 10.1
0.025 0.031 0.036 0.635 0.80 0.952 0.510 0.520 0.530 12.95 13.2 13.45 0.510 0.520 0.530 12.95 13.2 13.45 0.025 0.031 0.037 0.65 0.051 0.063 0.075 1.295 0.003 0 7 0 0.8 1.6 0.95 1.905 0.08 7
A2 A A1 y L L1 Detail F
Seating Plane
See Detail F
1. Dimension D & E do not include interl flash. 2. Dimension b does not include damb protrusion/intrusion. 3. Controlling dimension: Millimete 4. General appearance spec. should be ba on final visual inspection spec
- 20 -
W78C52D/W78C052D
12. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 A2 A3 A4 A5
December 1998 April 20, 2005 December 27, 2005 October 3, 2006 December 4, 2006
19 2 13 2
Initial Issued Add Important Notice Remove "Preliminary" from sheet header Add lead-free(RoHS) parts, Remove 24MHz parts Amend 24MHz as 40MHz Remove block diagram Remove all Leaded package parts
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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Publication Release Date: December 4, 2006 Revision A5

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